Capacitive micro-machined ultrasonic transducer (CMUT) devices are rapidly gaining popularity as the sensors in a range of sensing apparatuses such as imaging apparatuses. This is because CMUT devices can offer excellent bandwidth and acoustic impedance characteristics, which makes them the preferable over e.g. piezoelectric transducers.
Vibration of the CMUT membrane can be triggered by applying pressure (for example using ultrasound) or can be induced electrically. Electrical connection to the CMUT device, often by means of an integrated circuit (IC) such as an application specific integrated circuit (ASIC) facilitates both transmission and reception modes of the device. In reception mode, changes in the membrane position cause changes in electrical capacitance, which can be registered electronically. In transmission mode, applying an electrical signal causes vibration of the membrane.
CMUT devices generally operate with a biasing voltage applied. The CMUT can be operated in so called collapsed mode where the biasing voltage applied is increased above the collapse voltage to restrict the membrane and confine part of it against the substrate. The frequency of operation of the CMUT device is characterised by the material and physical properties of the membrane, such as the stiffness, and the size of the cavity. The bias voltage and application of the CMUT device also influence the operation mode. A CMUT device is often used in apparatuses for ultrasound imaging applications and in other applications where the CMUT device is used to detect fluid or air pressures. A pressure causes a deflection of the membrane that is electronically sensed as a change of capacitance. A pressure reading can then be derived.
FIG. 1 schematically depicts a top view and FIG. 2 schematically depicts a cross-section along the line A-A′ in FIG. 1 of a conventional CMUT device 1. The CMUT device comprises a plurality of CMUT cells 100 in a CMUT region 10 of the device 1 and a plurality of interconnects 200, which plurality may include routing lines 205, in an interconnect region 20 of the device 1. The boundary between the CMUT region 10 and the interconnect region 20 is indicated by the vertical dashed lines in FIG. 2. The interconnects 200 typically provide an interconnection to a conductive contact 210 such as a bond pad inside the CMUT device 1. Such conductive contacts may provide a connection to the outside world or may be used to facilitate interconnections between different elements of the CMUT device 1, e.g. between different CMUT cells 100, between a CMUT cell 100 and a signal processing element, and so on.
Each CMUT cell 100 typically comprises a first electrode 110 separated from a second electrode 120 by a cavity 130. The second electrode 120 is typically embedded in a membrane 140 made of one or more electrically insulating or dielectric layers. In some designs, the second electrode 120 is embedded in the membrane 140, i.e. sandwiched in between a relatively thin dielectric layer portion 142 and a relatively thick dielectric layer portion 144 from the cavity 130 to prevent a short circuit between the first electrode 110 and the second electrode 120 upon deformation of the membrane 140 including the second electrode 120 towards the first electrode 110.
Conventional CMUT designs have membrane 140 layer thicknesses in the order of 1-2 micron, which can be processed with common fabrication methods such as plasma-enhanced chemical vapour deposition (PECVD). However, where the CMUT cells 100 are required to operate at a low frequency, the membrane diameter D may need to be in excess of 100 micron, which can result in the thickness of the membrane 140 becoming larger than 3 micron. Consequently, the overall thickness of the dielectric layer stack in the interconnect region 20 on top of the conductive contacts 210, e.g. bond pads, may exceed 6 micron. This overall thickness may further increase, for instance when the substrate 30 on which the CMUT cells 100 comprises planarization and/or encapsulation layers, with the conductive contacts 210, e.g. bond pads, being formed underneath these additional layers, e.g. in the top metallization layer of a metallization stack. Such additional layers can add another 2-3 micron to the overall thickness of the dielectric layer stack.
In order to make an electrical connection to the CMUT and ASIC electrodes, the conductive contacts 210 are provided in the interconnect region 20 of the CMUT device 1, which region for instance may be located at the perimeter of the die. The conductive contacts 210 are typically made of a conductive material, for instance a metal such as aluminium, and are initially covered by the electrically insulating layers of the dielectric layer stack. To allow electrical connection to the conductive contacts 210, the conductive contacts 210 are typically etched open in one of the final phases of CMUT fabrication to form trenches 22, which trenches 22 are subsequently lined or filled with a metal interconnect 200.
However, the opening of the conductive contacts 210 in the interconnect region 20 of the CMUT devices 1 can become challenging if the overall thickness of the dielectric layer stack covering the conductive contacts 210 becomes too large, i.e. more than 2 micron. This typically requires an increase in the required etching time in order to etch through such thick dielectric layers. However, the maximum allowable etching time may be limited by selectivity and resist consumption issues. These conflicting requirements may make it impossible to fabricate CMUT devices 1 with thick membrane layers 140 in a conventional way.
A further challenge is that metallization of the conductive contacts 210 with thick metal interconnects 200 may become a challenge if the aspect ratio, i.e. the height H over the width W of the metal interconnects 200, becomes unfavourable. This is especially important if the metal interconnects 200 are used for I/O routing, as such routing needs to carry high currents, and therefore needs to be implemented with a relatively thick metal interconnect 200 to reduce resistivity. For such I/O routing, conductive contacts 210 and the metal interconnects 200 require a low-resistive electrical connection between each other. This therefore requires the trenches in which the metal interconnects are to be formed to be effectively lined or filled with the metal. However, such an effective lining or filling can be challenging for trenches having steep and deep sidewalls, i.e. having high aspect ratios.
Consequently, the manufacturing of CMUT devices that meet design specifications is a non-trivial exercise. In order to obtain cost-effective devices, it is for instance desirable to manufacture the CMUT devices in existing manufacturing technologies. CMOS is a non-limiting example of such a technology. U.S. Pat. No. 8,309,428 B2 for instance discloses a CMOS manufacturing method of such a device.
However, it proves to be difficult to obtain high yields of acceptable CMUT devices from wafers manufactured in such technologies, in particular when the individual CMUT cells have a relatively large diameter, such as diameters in excess of 100 microns, which for instance is required when the CMUT device is to be operated in a low-frequency mode.